module ctrl(
   input clk,
	input reset_n,
	input [15:0]ram_rd_data,
	output reg [15:0]ram_rd_addr,
	output reg clk_r,
	
	output	reg [19:0]	 	addr_t,
	output 	reg [15:0]		data_t,
	
	output	reg	 			req_t,
   //to top
	input 					busy

);


 parameter ram_pixel_num = 16'd9600;//ram里的像素总个数
 parameter pixel_num = 17'd76800;//ram里的像素总个数
 //parameter pixel_num = 17'h12c00;//ram里的像素总个数


 reg [8:0]j;
 

always@(posedge clk or negedge reset_n)
	if(!reset_n)
	begin 
		j <= 9'd0;
		clk_r <= 1'b0;
		addr_t <= 16'd0;
		req_t <= 1'b0;
		ram_rd_addr <= 16'd0;
	end
	else 
		case(j)
		
		0: begin   req_t <= 1'b0;  j  <= j + 1'b1; end
		
		1:if(addr_t < pixel_num) begin j  <= j + 1'b1;   end  
        else begin   j  <= j ;   end		
		
		
		2:if(ram_rd_addr < ram_pixel_num) begin j  <= j + 1'b1;   end  
        else begin   ram_rd_addr <= 16'd0 ;   end		
		
		
		3: if(!busy)    begin j  <= j + 1'b1;  end
		 else begin j  <= j ;    end
		
		4: begin clk_r <= 1'b0;j <= j + 1'b1;end

		5:begin clk_r <= 1'b1;j <= j + 1'b1;end

      6:begin data_t <= ram_rd_data;  ram_rd_addr <=  ram_rd_addr + 1'b1;  j <= j + 1'b1; end
	
		7:begin  req_t <= 1'b1; j <= j + 1'b1; end
		
		//已经读取到数据了，可以addr+1了
		8:if(busy)begin  addr_t <= addr_t + 1'b1; j <= 9'd0;end  
        else begin  j <= j;    end		
		
		
		
		
		
		
	endcase
	



 

endmodule
